1. Field of the Invention
The present invention relates to a semiconductor memory device or a semiconductor device, and relates to, e.g., an electrically rewritable NAND type EEPROM (an electrically erasable and programmable ROM) including memory cells each having a control gate and a floating gate.
2. Description of the Related Art
In recent years, as an electrically rewritable non-volatile semiconductor memory device, an NAND type EEPROM is used in various kinds of devices. The NAND type EEPROM has a plurality of NAND type memory cells connected in series (which will be referred to as NAND cells hereinafter) and selection gate transistors arranged at both ends of each NAND cell. The selection gate transistors are positioned at both ends of each NAND cell. When the selection gate transistor alone connected with the NAND cell at a selected address is turned on, selection/non-selection of the NAND cell is defined.
A high-voltage pulse at the time of a write operation or a high-speed pulse at the time of a read operation is applied to a word line adjacent to a gate electrode (which will be referred to as a selection gate hereinafter) of the selection gate transistor. In such a case, when a selection gate potential of the selection gate transistor is affected to fluctuate, characteristics of the above-described selection/non-selection are deteriorated. Therefore, the selection gate of the selection gate transistor is backed (shunted) by a metal wiring line having a lower resistance in a cell array (see, e.g., Jpn. Pat. Appln. KOKAI Publication No. 2000-91546). Since the metal wiring line is formed in an upper late of the selection gate, a contact material which connects the metal wiring line with the selection gate is required. A region in which the contact material which connects the metal wiring line with the selection gate is formed in order to reduce a resistance of the selection gate in this manner will be referred to as a shun region hereinafter.
In case of forming the contact material on the selection gate in the shunt region, there is concern that a gate insulating film immediately below the contact material is damaged due to a mechanical stress during processing or a stress due to boring a gate material, and there occurs a problem that noise of a selection gate potential is thereby increased.
Further, in a transistor constituting a peripheral circuit, there is likewise concern that a gate insulating film immediately below a contact material is damaged when forming the contact material on a gate electrode, and hence a gate electrode region in which the contact material is arranged is required on an element isolation region. Therefore, there occurs a problem that an area required for formation of the transistor cannot be reduced.